
module REG_MEM_WB(
    input clk,
    input rst_n,
    
    input rf_we_in,
    input [4:0] wR_in,
    input [31:0] wD_in,
    
    output reg rf_we_out,
    output reg [4:0] wR_out,
    output reg [31:0] wD_out,
    
    input      [31:0] pc_in,
    output reg [31:0] pc_out,
    input             debug_have_inst_in,
    output reg        debug_have_inst_out
    );
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  pc_out <= 32'b0;
        else        pc_out <= pc_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  debug_have_inst_out <= 1'b0;
        else        debug_have_inst_out <= debug_have_inst_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      rf_we_out <= 1'b0;
        else            rf_we_out <= rf_we_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wR_out <= 5'b0;
        else            wR_out <= wR_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wD_out <= 32'b0;
        else            wD_out <= wD_in;
    end

endmodule
